Linear signal amplification represents a core enabling function in most communication circuits. For example, wireless communication transceivers employ linear signal amplification at various stages in their transmit and receive signal processing paths. More particularly, radiofrequency (RF) based communication systems rely on linear amplification in frequency mixing circuits, low-noise amplification circuits, power amplification circuits, and the like, to maintain signal fidelity and to limit the generation of unwanted harmonic frequencies. However, the non-linear current-voltage (IV) behavior of semiconductor transistors, such as bipolar or MOS transistors, represents a fundamental source of signal non-linearity in communication circuits, which rely heavily on the use of such transistors.
Important transistor-related parameters for most analog RF building blocks include transconductance, noise, and output conductance. In particular, transistor transconductance (gm), a derivative of the drain-source/collector current with respect to the gate-source/base-emitter voltage, represents a fundamental measure of transistor linearity. The first derivative of the drain-source/collector current with respect to the gate-source/base-emitter voltage (gm1) represents the linear coefficient of the transistors. The second and third derivatives of the drain-source/collector current with respect to the gate-source/base-emitter voltage (gm2 and gm3) represent respectively the second and third-order nonlinearity coefficients of the transistors. The nonlinearity coefficients gm2 and gm3 affect 2nd and 3rd-order inter-modulation distortion (IMD2 and IMD3) which in turn affect the 2nd and 3rd-order intercept points (IP2 and IP3). Higher IP2 and IP3, that is higher linearity of the circuit, require gm2 and gm3 to be zero or close to zero.
Heterodyne and homodyne are two typical receiver architectures in wireless communication transceivers. The homodyne receiver has taken over today in the highly integrated circuit (IC) implementations. It turns out that in general these two receivers are sensitive to different types of nonlinear distortion. The second-order nonlinearity in transistors generates second-order distortion signals which can be difficult to distinguish from the desired signal in the homodyne receiver. Similar arguments can be made for the heterodyne receiver which has high requirements on the third-order nonlinear distortion. For modern radio transceivers in general, especially those handling multi-standards, there are requirements on both second and third-order nonlinearities since there are signals with different frequencies present at the receiver and different frequency combinations occur. It is thus of interest to reduce both 2nd and 3rd order nonlinear distortion at the same time.
There are many different linearization techniques, such as feedback, pre-distortion and poly-phase filtering which may be used in order to compensate for transistor device nonlinearity. More fundamental nonlinearity compensation mechanisms exist apart from or in conjunction with these compensation techniques. For example, a more linear composite transistor device can be formed by placing two or more transistors in parallel, such as in U.S. Pat. No. 6,636,115; U.S. Pat. No. 6,819,184 and Chunyu Xin et al “a Linearization Technique for RF Low Noise Amplifier”, paper from IEEE International Symposium on Circuit And Systems 2004, techniques are exploited for nonlinearity cancellation of a transistor pair by different gate/base biasing and properly sizing the transistors. However the cancellation only applies for the third-order or odd-order nonlinearity. Chunyu Xin et al state in “a Linearization Technique for RF Low Noise Amplifier” that the second-order nonlinearity usually gets worse for the best third-order distortion cancellation bias point. This is due to the fact that for different gate bias, although the 3rd-order coefficients of the two transistors can have different signs, they can be cancelled out by combining the current, the 2nd-order coefficients, however will have the same sign. By adding the output currents of the transistor pair, the 2nd-order term will be added so it deteriorates the second-order intercept point IP2. In order to keep IP2 performance and at the same time provide third-order compensation, a differential circuit with matched transistors is used so that the 2nd-order distortion can be cancelled. However, differential circuits are complicated and have high current consumption, and in addition require perfectly matched transistors.
U.S. patent publication No. 2005/0176399 presents an amplifier which comprises a source degeneration inductance and at least two field effect transistors coupled in parallel and having mutually different gate biasing. Source connections of the field effect transistors are coupled along different positions of the source degeneration inductance. This technique is used to reduce the contribution of the second-order nonlinearity to the third-order intermodulation distortion for high frequencies when the composite transistor is biased for optimum third-order nonlinearity cancellation. The cancellation of second-order nonlinearity itself is not discussed.
Therefore there is a need to exploit a method and circuitry that can cancel both 2nd and 3rd-order nonlinearities at the same time, that is to say, to improve IP2 and IP3 simultaneously.